Scalable disc array controller

ABSTRACT

This invention relates to a disk array controller. There has been demand for a large scale memory device system operable without interruption. Further, in order to cope with the recent trend toward open systems, scalability of performance and capacity in such systems is needed. 
     Conventionally, internal buses such as ones which connect the channel interface section to the shared memory section, and the disk interface section to the shared memory section, have been mounted on one platter, and the channel interface and other packages have been mounted thereon. If the internal buses have failed, the operation of the whole system must be stopped. There has been another problem that the performance of the internal buses is fixed. 
     A disk array controller according to this invention comprises an interface platter on which a channel interface section and a disk interface section are mounted, a memory platter on which a shared memory section is mounted, and a cable which connects the interface platter to the memory platter in order to solve the above problems.

This application claims benefit of priority of PCT ApplicationPCT/JP98/02176 filed on May 18, 1998 in Japan.

TECHNICAL FIELD

This invention relates to a controller for a disk array device whichdivides data and stores it in plural magnetic disk drives.

BACKGROUND ART

The I/O performance of subsystems which use magnetic disk drives assecondary memories is lower than that of computer main memories by threeor four digits. Efforts to minimize this performance discrepancy orimprove the I/O performance of subsystems have been made by many people.As one method for improving the I/O performance of subsystems, what iscalled a disk array, in which a subsystem is composed of plural magneticdisk drives and data is divided and stored in the magnetic disk drives,has been known.

In one example of the prior art, as shown in FIG. 2, a disk array devicehas the following: plural channel interface units 111 for datatransmission between a host computer 101 and a disk array controller 5;plural disk interface units 112 for data transmission between magneticdisk drives 120 and the disk array controller 5; a cache memory unit 115which temporarily stores data to be recorded in the magnetic disk drives120; and a shared memory unit 114 which stores control data for thecache memory unit 115 and the disk array controller 5, where the cachememory unit 115 and the shared memory unit 114 are accessible from allthe channel interface units 111 and all the disk interface units 112. Inthis conventional system, each of the channel interface units 111 andthe disk interface units 112 is connected to the shared memory unit 114or to the cache memory unit 115.

In another example of the prior art, as shown in FIG. 3, a disk arraydevice has the following: plural channel interface units 111 for datatransmission between a host computer 101 and a disk array controller 6;plural disk interface units 112 for data transmission between magneticdisk drives 120 and a disk array controller 6; cache memory units 115which temporarily store data to be recorded in the magnetic disk drives120; and shared memory units 114 which store control data for the cachememory units 115 and the disk array controller 6, where each of thechannel interface units 111 and the disk interface units 112 isconnected to the shared memory units 114 through a shared bus 130 andeach of the channel interface units 111 and the disk interface units 112is connected with the cache memory units 115 though a shared bus 130.

DISCLOSURE OF THE INVENTION

Large scale memory systems which are used for data management of maincomputer systems in large scale companies such as banks, securitiescompanies and telephone companies are required to run around the clockuninterruptedly all the year round. In addition, with the recent growingdemand for open-ended systems, scalability of performance and capacityis anticipated to support small to large scale systems.

However, in the prior art shown in FIGS. 2 and 3, the internal buseswhich connect each of the channel interface units 111 and disk interfaceunits 112 to the shared memory unit 114 or to the cache memory unit 115are mounted on one platter (backplane), and channel interface packagesand disk interface packages are mounted on the same platter. Due to thisstructure, in the case of a fault in the internal buses, the platteritself had to be replaced, which means that the whole system had to bestopped.

Besides, since the internal buses are mounted on the platter, theirperformance is fixed. Therefore, the prior art has the followingproblem: in small scale systems, the cost performance is low because theperformance of the internal buses is too high to match that of thechannel or disk interface units, while in large scale systems, theperformance of the internal buses is insufficient and cannot beincreased.

As there is a drastic decline in the price of large disk array devicesin the market, products with higher cost performance are anticipated.

A first object of the present invention is to provide a disk arraycontroller which runs around the clock all the year arounduninterruptedly without the need for stopping the whole system in thecase of a fault or during maintenance. A second object of the presentinvention is to provide a disk array controller which providesscalability of performance and capacity without an unfavorable influenceon the cost performance.

The above-mentioned objects can be achieved by a disk array controllerwhich has the following: an interface unit platter on which channelinterface units connected with the host computer and disk interfaceunits connected with disk drives are mounted; a memory platter on whicha shared memory unit for storing control data is mounted; and cableswhich connect the interface platter and the memory platter.

Also, the above-mentioned objects can be achieved by a disk arraycontroller which has the following: plural platters on each of whichchannel interface units connected with the host computer, disk interfaceunits connected with disk drives and a shared memory unit for storingcontrol data are mounted; and cables which interconnect the pluralplatters.

Furthermore, the above-mentioned objects can be achieved by a disk arraycontroller which has the following: an interface platter on whichchannel interface units connected with the host computer, disk interfaceunits connected with disk drives, shared buses which connect the channelinterface units and disk interface units, and shared bus interconnectcontrollers connected with the shared buses to control requests from thechannel interface units and the disk interface units, are mounted; amemory platter on which shared memory units for storing control data aremounted; and cables which connect the interface platter and the memoryplatter.

The above-mentioned disk array controller according to this inventionuses expensive cables. Further, data transmission at high frequencies bycables is likely to cause noise. Therefore, a further object of thisinvention is to shorten the cable length in the disk array controlleraccording to this invention which is placed in the rack, as far aspossible.

The above-said further object of the present invention can be achievedby a disk array controller which has the following: an interface platteron which channel interface units connected with the host computer, anddisk interface units connected with disk drives are mounted; and amemory platter on which shared memory units for storing control data aremounted, where the orientation of the mounted interface platter isdifferent from that of the mounted memory platter.

Also the above-said further object of the present invention can beachieved by a disk array controller which has the following: pluralinterface platters on each of which channel interface units connectedwith the host computer, and disk interface units connected with diskdrives are mounted; and a memory platter on which shared memory unitsfor storing control data are mounted, where the memory platter islocated between the plural interface platters.

Also, the above-said further object can be achieved by a disk arraycontroller which has plural platters on each of which channel interfaceunits connected with the host computer, disk interface units connectedwith disk drives, and a shared memory unit for storing control data aremounted, where one of the plural platters is located above another ofthem.

Other solutions for the above-mentioned objects and further object willbe discussed in the section “BEST MODE FOR CARRYING OUT THE INVENTION.”

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 shows a configuration in the rack-mounted form of a disk arraycontroller according to this invention.

FIG. 2 shows a configuration of a conventional disk array controller.

FIG. 3 shows a configuration of a conventional disk array controller.

FIG. 4 shows a configuration of a disk array controller according tothis invention.

FIG. 5 shows another configuration of a disk array controller accordingto this invention.

FIG. 6 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 7 shows another configuration of a disk array controller accordingto this invention.

FIG. 8 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 9 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 10 shows another configuration of a disk array controller accordingto this invention.

FIG. 11 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 12 shows another configuration of a disk array controller accordingto this invention.

FIG. 13 shows another configuration of a disk array controller accordingto this invention.

FIG. 14 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 15 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 16 show another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 17 shows another configuration of a disk array controller accordingto this invention.

FIG. 18 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 19 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 20 shows another configuration of a disk array controller accordingto this invention.

FIG. 21 shows another configuration of a disk array controller accordingto this invention.

FIG. 22 shows another configuration of a disk array controller accordingto this invention.

FIG. 23 shows another configuration of a disk array controller accordingto this invention.

FIG. 24 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 25 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 26 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 27 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 28 shows another configuration of a disk array controller accordingto this invention.

FIG. 29 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 30 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 31 shows another configuration of a disk array controller accordingto this invention.

FIG. 32 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 33 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 34 shows another configuration of a disk array controller accordingto this invention.

FIG. 35 shows another configuration of a disk array controller accordingto this invention.

FIG. 36 shows another configuration of a disk array controller accordingto this invention.

FIG. 37 shows another configuration of a disk array controller accordingto this invention.

FIG. 38 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 39 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 40 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 41 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 42 shows another configuration of a disk array controller accordingto this invention.

FIG. 43 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 44 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 45 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 46 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 47 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 48 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 49 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 50 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 51 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 52 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 53 shows another configuration of a disk array controller accordingto this invention.

FIG. 54 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 55 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 56 shows another configuration of a disk array controller accordingto this invention.

FIG. 57 shows another configuration of a disk array controller accordingto this invention.

FIG. 58 shows another configuration of a disk array controller accordingto this invention.

FIG. 59 shows another configuration of a disk array controller accordingto this invention.

FIG. 60 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 61 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 62 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 63 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 64 shows another configuration of a disk array controller accordingto this invention.

FIG. 65 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 66 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 67 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 68 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 69 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 70 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 71 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 72 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 73 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 74 shows another configuration in the rack-mounted form of a diskarray controller according to this invention.

FIG. 75 shows one form of implementation of platters in a disk arraycontroller according to this invention.

FIG. 76 shows another form of implementation of platters in a disk arraycontroller according to this invention.

FIG. 77 shows a rack housing a disk array controller according to thisinvention.

FIG. 78 shows another type of rack housing a disk array controlleraccording to this invention.

FIG. 79 shows another type of rack housing a disk array controlleraccording to this invention.

FIG. 80 shows connections between platters in a disk array controlleraccording to this invention.

FIG. 81 shows how interface platters in a disk array controlleraccording to this invention are mounted.

FIG. 82 shows how memory platters in a disk array controller accordingto this invention are mounted. and

FIG. 83 shows how power supplies of a disk array controller according tothis invention are mounted.

BEST MODE FOR CARRYING OUT THE INVENTION

The best mode for carrying out this invention is explained next usingvarious embodiments.

Embodiment 1

FIGS. 1 and 4 show one embodiment of the invention.

FIG. 4 shows the configuration of a disk array controller according tothe invention. The disk array controller 1 has channel interface units111, disk interface units 112, shared memory units 114 and access paths0 (135).

The channel interface units 111 each have at least one interface withthe host computer, at least one microprocessor, at least one (two, inthis embodiment) access circuit to the shared memory units 114, and atleast one (two, in this embodiment) access path interfaces to the sharedmemory units 114 (these are not shown here) to enable data transmissionbetween the host computer 101 and the shared memory units 114.

The disk interface units 112 each have at least one interface withplural magnetic disk drives 120, at least one microprocessor, at leastone (two, in this embodiment) access circuit to the shared memory units114, and at least one (two, in this embodiment) access path interfacewith the shared memory units 114 (these are not shown here) to enabledata transmission between the plural magnetic disk drives 120 and theshared memory units 114.

The shared memory units 114 each have a memory for storing data to berecorded in the magnetic disk drives 120, control data for that data andcontrol data for the disk array controller 1, and at least one (eight,in this embodiment) access path interfaces (these are not shown here) tothe interface units.

In this embodiment, two channel interface units 111 and two diskinterface units 112 constitute one group, which is called an I/F group160. In this embodiment, the disk array controller 1 has two I/F groups.

Here, the number of I/F groups 160 is not limited as above. The numberof I/F groups depends on the number of access paths to the shared memoryunits, management unit for maintenance (the number of channel and diskinterface units subjected to each maintenance service), and otherfactors. One possibility is that the minimum disk array controllerconfiguration corresponds to one I/F group.

FIG. 1 illustrates the configuration of the disk array controller 1 inthe rack-mounted form. The channel interface units 111, disk interfaceunits 112 and shared memory units 114 shown in FIG. 4 are separatelypackaged in channel interface packages (PK) 11, disk interface packages(PK) 12 and shared memory packages (PK), respectively. The channelinterface packages 11 and disk interface packages 12 which constituteone I/F group 160, are mounted on one interface platter (P/L) 2, and thetwo shared memory packages 14 are mounted on a memory platter (P/L) 3different from the interface platters 2. Each interface platter 2 andthe memory platter 3 are connected by a cable 4. The cable 4 is a cablefor access path 0 (135) which connects the channel interface units 111or disk interface units 112 with the shared memory units 114.

The channel interface packages 11, disk interface packages 12, andshared memory packages 14 may be all mounted on different platters.

As described above, when a certain number of interface packages aremounted on one interface platter, in case of a fault in a platter, it isonly necessary to stop the parts for which the packages mounted on thatplatter are responsible, instead of stopping the entire system. Also,since the cable 4 is used for the access paths 0 (135), the number ofaccess paths 0 (135) can be easily increased or decreased as the numberof interface platters 2 bearing interface packages increases ordecreases, so that scalability of access path 0 performance can beassured. Therefore, the performance and capacity can be flexibly varieddepending on the scale of the system, without any deterioration in costperformance. This also implies that a disk array controller product canbe supplied at a reasonable price which suits the scale of the system.

Embodiment 2

FIGS. 31 and 32 show another embodiment of this invention. Itsdifference from embodiment 1 is that the two shared memory units 114 inFIG. 4 are interconnected via access path 2 (139) to make a dual system,as shown in FIG. 31.

FIG. 32 illustrates the configuration of the disk array controller 1 inFIG. 31 in the rack-mounted form. Two shared memory units 114 areseparately packaged in two shared memory packages (PK) 14, which aremounted on different memory platters 3. The memory platters 3 areinterconnected by cable 2 (4-9) and one interface platter 2 and each ofthe two memory platters 3 are connected by cable 4. The cable 2 is acable for access path 2 (139) as shown in FIG. 31.

This configuration not only produces the same effects as those ofembodiment 1 but also a further effect: Thanks to the dual system ofshared memory units 114, even if one shared memory package 14 or memoryplatter 3 fails, the system can be operated using the shared memorypackage 14 mounted on the other memory platter 3. Therefore, it ispossible to replace the defective shared memory package 14 or memoryplatter 3, without stopping the system.

In this embodiment, the shared memory units 114 are interconnected viaaccess path 2 (139) to make a dual system; however, instead, the samedual system effect can be obtained by writing the same data in both thetwo shared memory units 114 from the channel interface units 111 or diskinterface units 112. In this case, it is unnecessary to interconnect theshared memory units 114 via access path 2 (139). However, if they areinterconnected via access path 2 (139), the data in the two sharedmemory units 114 can be directly cross-checked for confirmation or asimilar purpose, resulting in improved reliability.

Embodiment 3

FIG. 45 shows another embodiment of the invention. Like embodiment 2,this embodiment uses two shared memory units 114 which make up a dualsystem. Two shared memory units 114 are separately packaged in sharedmemory packages 14, which are mounted on one memory platter 3. Thismemory platter 3 is divided into two areas by a power supply boundary300. Power is separately supplied from independent power supplies to thetwo areas. Each of the areas bears one shared memory package 14. Oneinterface platter 2 and the two areas of the memory platter 3 areconnected by cables 4.

This configuration not only produces the same effects as those ofembodiment 1 but also a further effect: even if a fault occurs in theshared memory package 14 in one of the areas into which the memoryplatter 3 is divided by the power supply boundary 300, the system can beoperated using the shared memory package 14 mounted on the other area.Therefore, it is possible to replace the defective shared memory package14, without stopping the system.

Embodiment 4

FIGS. 17 and 18 show another embodiment of the invention. Its differencefrom embodiment 1 is that as shown in FIG. 17, the cache memory units115 for storing data to be recorded in magnetic disk drives 120, and theshared memory units 114 for storing control data for the cache memoryunits 115 and the disk array controller 1 are physically divided, andaccess paths a (137) to the shared memory units 114, and access paths b(138) to the cache memory units 115 are independent of each other.

FIG. 18 illustrates the configuration of the disk array controller 1 inFIG. 17 in the rack-mounted form. The cache memory units 115 and theshared memory units 114 are separately packaged in cache memory packages15 and shared memory packages 14, respectively, which are mounted on thememory platter 3. In place of the cable 4 which connects each interfaceplatter 2 and the memory platter 3 as shown in FIG. 1, cables a (4-3)for access paths a (137) to the shared memory units 114 and cables b(4—4) for access paths b (138) to the cache memory units 115 are used.

The shared memory packages 14 and the cache memory packages 15 may bemounted on different platters.

This configuration not only produces the same effects as those ofembodiment 1 but also a further effect: Since access paths from thechannel interface packages 11 and the disk interface packages 12 to thecache memory packages 15 or the shared memory packages 14 can be madephysically independent, it is possible to distinguish between faultsrelated to access to the cache memory units 115 (faults in the cachememory units 115 or paths or others for access to them) and faultsrelated to access to the shared memory units 114 (faults in the sharedmemory units 114 or paths or others for access to them) so thatdefective parts can be independently repaired without affecting otherparts.

Embodiment 5

FIGS. 53 and 54 show another embodiment of this invention. Itsdifference from embodiment 4 is that two shared memory units 114 areinterconnected via access path a2 (140) and two cache memory units 115are interconnected via access path b2 (141) to make a dual system, asshown in FIG. 53.

FIG. 54 illustrates the configuration of the disk array controller 1 inFIG. 53 in the rack-mounted form. Two shared memory units 114 and twocache memory units 115 are separately packaged in shared memory packages14 and cache memory packages 15, respectively, and one shared memorypackage and one cache memory package, which constitute one set, aremounted on one memory platter 3, with the two memory platters 3 beinginterconnected by cable a2 (4-10) and cable b2 (4-11). One interfaceplatter 2 is connected to two memory platters 3 by cable a (4-3) andcable b (4—4). Cable a2 (4-10) and cable b2 (4-11) are cables for accesspath a2 (140) and access path b2 (141), respectively.

This configuration not only produces the same effects as those ofembodiment 4 but also a further effect: Even if a fault occurs in oneshared memory package 14, cache memory package 15 or memory platter 3,the system can be operated using the shared memory package 14 or cachememory package 15 mounted on the other memory platter 3. Therefore, itis possible to replace the defective shared memory package 14, cachememory package 15 or memory platter 3, without stopping the system.

In this embodiment, the shared memory units 114 are interconnected viaaccess path a2 (140) and the cache memory units 115 are interconnectedvia access path b2 (141); however, instead, the same dual system effectcan be obtained by writing the same data in both the two shared memoryunits 114 or both the two cache memory units 115 from the channelinterface units 111 or the disk interface units 112. In this case, it isunnecessary to interconnect the shared memory units 114 or the cachememory units via access path a2 (140) or access path b2 (141). However,if they are interconnected via access path a2 (140) or access path b2(141), the data in the two shared memory units 114 or the two cachememory units 115 can be directly cross-checked for confirmation or asimilar purpose, resulting in improved reliability.

Embodiment 6

FIG. 67 shows another embodiment of the invention. As shown in FIG. 67,in this embodiment, two shared memory units 114 and two cache memoryunits 115 are packaged in shared memory packages 14 and cache memorypackages 15, respectively, which are mounted on one memory platter 3which is divided into two areas by a power supply boundary 300 as inembodiment 3. Each of the areas bears one shared memory package 14 andone cache memory package 15. One interface platter 2 is connected to oneof the two areas of the memory platter 3 by cables a (4-3) and to theother by cables b (4—4). This embodiment thus provides a dual systemwhich consists of two shared memory units 114 and two cache memory units115.

This configuration not only produces the same effects as those ofembodiment 4 but also a further effect: Even if a fault occurs in theshared memory package 14 or cache memory package 15 in one of the areasinto which the memory platter 3 is divided by the power supply boundary300, the system can be operated using the shared memory package 14 orcache memory package 15 in the other area of the memory platter 3.Therefore, it is possible to replace the shared memory package 14 orcache memory package 15 in the area where the fault has occurred,without stopping the system.

Embodiment 7

FIG. 5 shows another embodiment of the invention. The disk arraycontroller 1 shown in FIG. 5 has the following: channel interface units111; disk interface units 112; two shared buses 0 (31) which connectthem; shared memory units 114; two shared buses 1 (32) whichinterconnect the shared memory units; shared bus interconnectcontrollers 140 which connect the shared buses 0 (31) and shared buses 1(32); and access paths 0 (135).

Each channel interface unit 111 has at least one interface with the hostcomputer, at least one microprocessor, at least one (two, in thisembodiment) access circuit to the shared memory unit 114, and at leastone (two, in this embodiment) interface with the shared buses 0 (31)(these are not shown here) to enable data transmission between the hostcomputer 101 and the shared memory units 114.

Each disk interface unit 112 has at least one interface with pluralmagnetic disk drives 120, at least one microprocessor, at least one(two, in this embodiment) access circuit to the shared memory units 114,and at least one (two, in this embodiment) interface with the sharedbuses 0 (31) (these are not shown here) to enable data transmissionbetween the plural magnetic disk drives 120 and shared memory units 114.

Each shared memory unit 114 has a memory for storing data to be recordedin the magnetic disk drives 120, control data for that data and controldata for the disk array controller, and at least one (two, in thisembodiment) interface with shared buses 1 (32) (these are not shownhere).

One shared bus is connected with one shared bus interconnect controller140. The shared bus interconnect controllers 140 connected with theshared buses 1 (32) each have two access paths 0 (135) from two sharedbus interconnect controllers 140 which belong to different I/F groups160.

For access from the channel interface units 111 or disk interface units112 to the shared memory units 114, the SM access circuit (not shownhere) inside each channel interface unit 111 or disk interface unit 112first obtains the right to use the shared buses 0 (31) and then accessesthe shared bus interconnect controller 140 connected with the sharedbuses 0 (31), and issues a request for access to the shared buses 1(32). The shared bus interconnect controller 140 sends the accessrequest to the shared bus interconnect controller 140 connected with theshared buses 1 (32). If the shared bus interconnect controller 140connected with the shared buses 1 (32) receives access requests from twodifferent shared bus interconnect controllers 140 connected with it, itselects one of them by arbitration and obtains the right to use theshared buses 1 (32). After obtainment of the right, the shared businterconnect controller connected with the shared buses 1 (32) sends theaccess request to the shared memory units.

In this embodiment, two channel interface units 111, two disk interfaceunits 112 and two shared bus interconnect controllers 140 constitute onegroup, which is hereinafter called an I/F group 160. In this embodiment,the disk array controller 1 has two I/F groups.

Here, the number of I/F groups 160 is not limited as above. The numberof I/F groups depends on the management unit for maintenance (the numberof channel and disk interface units subjected to each maintenanceservice), and other factors. One possibility is that the minimum diskarray controller configuration corresponds to one I/F group. Though thisembodiment uses two shared buses 0 (31), it is possible to use only one.However, the use of two shared buses like this makes the access path tothe shared memory units 114 redundant, which improves troubleresistance.

The configuration of the disk array controller 1 in FIG. 5 in therack-mounted form is basically the same as the configuration ofembodiment 1 shown in FIG. 1. The difference from embodiment 1 is thatshared buses 0 (31) are wired on interface platters 2 and shared businterconnect controllers 140 are directly mounted there, and that sharedbuses 1 (32) are wired on one memory platter and shared bus interconnectcontrollers 140 are directly mounted there.

The advantage of this configuration is as follows. The use of cables asaccess paths would be more costly than when access paths are directlymounted on a platter. Further, data transmission at high frequencies byseveral cables could cause noise unless the cable length is equalizedwith high accuracy. It is more advantageous in terms of scalability touse cables for all access paths between the channel interface packages11, disk interface packages 12 and shared memory package 14 as in thedisk array controller of embodiment 1. However, for the above-mentionedreason, the use of many cables may be disadvantageous in terms of costand implementation efficiency. Therefore, in this embodiment the numberof cables used is decreased in comparison with the disk array controllerof embodiment 1 by wiring shared buses 0 (31) on interface platters 2and directly mounting shared bus interconnect controllers 140 thereon,and wiring shared buses 1 (32) on one memory platter and directlymounting shared bus interconnect controllers 140 thereon. This realizesa disk array controller which has an advantage over the prior art interms of scalability and over the disk array controller of embodiment 1in terms of cost and implementation efficiency.

In addition, since this embodiment uses a dual system consisting of twoshared buses 0 (31), two shared buses 1 (32) and shared bus interconnectcontrollers 140 connected with them, one channel interface unit 111 ordisk interface unit 112 has two access routes to one shared memory unit114. Therefore, in this embodiment, one cable 4 as shown in FIG. 1 isreplaced by two cables, each of which is allocated to one of the twoaccess paths 0 (135). Thanks to this dual system, if one of the twoaccess paths 0 (135) fails, the other access path 0 (135) can be used,permitting the system to operate uninterruptedly. During operation ofthe system, the cable 4 for the defective access path 0 (135) can bereplaced.

Embodiment 8

FIG. 34 shows another embodiment of this invention. In the disk arraycontroller 1 as shown in FIG. 34, two shared memory units 114 connectedwith two shared buses 1 (32) and two shared bus interconnect controllers140 constitute one group. Two such groups make up shared memory. The twoshared memory units in one group and those in the other group areconnected via access paths 2 (139) to make a dual system. In short, thisembodiment doubles the group of shared memory units 114 as shown in FIG.5 for embodiment 7.

The configuration of the disk array controller 1 in FIG. 34 in therack-mounted form is the same as the configuration shown in FIG. 32 forembodiment 2, except that the four shared memory units 114 areseparately packaged in shared memory packages 14, which are mounted ontwo different memory platters 3 group by group. Therefore, in thisembodiment, since one such group contains two shared memory units 114,one memory platter 3 bears two shared memory packages 14 (FIG. 32 showsonly one shared memory package 14 on each platter). In this respect,this embodiment is different from embodiment 2. Another difference fromembodiment 2 is that shared buses 1 (32) are wired on the memoryplatters 3 and two shared bus interconnect controllers are directlymounted thereon (these are not shown here).

The above-mentioned configuration produces the same effects as those ofembodiments 2 and 7.

In this embodiment, the shared memory units 114 are interconnected viaaccess paths 2 (139) to make a dual system; however, instead, the samedual system effect can be obtained by writing the same data in both thetwo shared memory units 114 from the channel interface units 111 or diskinterface units 112. In this case, it is unnecessary to interconnect theshared memory units 114 via access paths 2 (139). However, if they areinterconnected via access paths 2 (139), the data in the two sharedmemory units 114 can be directly cross-checked for confirmation or asimilar purpose, resulting in improved reliability.

The above-said groups of shared memory units 114 may be mounted in thesame way as shown in FIG. 45 for embodiment 3. In other words, each ofthe above groups of shared memory units 114 is mounted on each of thetwo areas of one memory platter 3 divided by a power supply boundary300, to which power is supplied from separate power supplies.

Thanks to this configuration, even if a fault occurs in a shared memorypackage 14 in one of the areas into which the memory platter 3 isdivided by the power supply boundary 300, the system can be operatedusing the shared memory packages 14 mounted on the other area, so thedefective shared memory package 14 can be replaced without stopping thesystem.

Embodiment 9

FIG. 20 shows another embodiment of this invention. According to thisembodiment, the cache memory units and shared memory units in the diskarray controller shown in FIG. 5 for embodiment 7 are physically dividedas described for embodiment 4. Also, in this embodiment, the sharedbuses 0 (31) in FIG. 5 are divided into shared buses b0 (35) fortransmitting data from the magnetic disk drives 120 and shared buses a0(33) for transmitting control data for the cache memory units 115 anddisk array controller 1, and the channel interface units 111 and diskinterface units 112 are connected to both the shared buses a0 (33) andshared buses b0 (35). Further, the shared buses 1 (32) in FIG. 5 aredivided into shared buses b1 (36) for transmitting data from themagnetic disk drives 120 and shared buses a1 (34) for transmittingcontrol data for the cache memory units 115 and disk array controller 1,and the cache memory units 115 and shared memory units 114 are connectedto the shared buses b1 (36) and shared buses a1 (34), respectively.Connections are made between the shared buses a0 (33) and shared busesa1 (34), and between the shared buses b0 (35) and the shared buses b1(36) through shared bus interconnect controllers 140, via access paths a(137) and access paths b (138), respectively.

The configuration of the disk array controller 1 in FIG. 20 in therack-mounted form is the same as the one shown in FIG. 18 for embodiment4, except that the two cache memory units 115 and two shared memoryunits 114 in FIG. 20 are separately packaged in two separate cachememory packages 15 and two shared memory packages 14, respectively,which are mounted on a memory platter 3. On the memory platter 3, theshared buses a1 (34) and shared buses b1 (36) are wired and the sharedbus interconnect controllers 140 are directly mounted thereon (all theseare not shown here). On each interface platter 2, the shared buses a0(33) and shared buses b0 (35) are wired and the shared bus interconnectcontrollers 140 are directly mounted thereon (all these are not shownhere). The cable which connects each interface platter 2 and memoryplatter 3 is divided into a cable a (4-3) for access path a (137) to theshared memory units 114 shown in FIG. 20 and a cable b (4—4) for accesspath b (138) to the cache memory units 115 in FIG. 20.

This configuration not only produces the same effects as those ofembodiment 7 but also a further effect: Since the access paths from thechannel interface packages 11 and disk interface packages 12 to thecache memory packages 15 or shared memory packages 14 are physicallyindependent, it is possible to distinguish between faults related toaccess to the cache memory units 115 (faults in the cache memory units115 or the shared buses b0 (35), shared buses b1 (36), shared businterconnect controllers 140, access paths b (138) or others for accessto them) and faults related to access to the shared memory units 114(faults in the shared memory units 114 or the shared buses a0 (33),shared buses a1 (34), shared bus interconnect controllers 140, accesspaths a (137) or others for access to them) so that defective parts canbe independently repaired without affecting other parts.

Embodiment 10

FIG. 56 shows another embodiment of this invention. As shown in FIG. 56,two shared memory units 114 connected with two shared buses a1 (34), andtwo shared bus interconnect controllers 140, constitute one group; twosuch groups make up shared memory. The two shared memory units 114 inone such group and those in the other group are connected via accesspaths a2 (140) to make a dual system. Two cache memory units 115connected with two shared buses b1 (36), and two shared bus interconnectcontrollers 140, constitute one group; two such groups make up cachememory. The two cache memory units 115 in one such group and those inthe other group are connected via access paths b2 (140) to make a dualsystem.

In short, this embodiment doubles the group of shared memory units 114and the group of cache memory units 115 as shown in FIG. 20 forembodiment 9.

The configuration of the disk array controller 1 in FIG. 56 in therack-mounted form is the same as the one shown in FIG. 54 for embodiment5, except that the four shared memory units 114 and four cache memoryunits 115 as shown in FIG. 56 are separately mounted in shared memorypackages 14 and cache memory packages 15, respectively, and one sharedmemory group and one cache memory group are mounted on one memoryplatter 3. On each memory platter 3, shared buses a1 (34) and sharedbuses b1 (36) are wired and four shared bus interconnect controllers 140are directly mounted. On each interface platter 2, shared buses a0 (33)and shared buses b0 (35) are wired and shared bus interconnectcontrollers 140 are directly mounted (all these are not shown here).Connection between the memory platters 3 is made by cables a2 (4-10) andb2 (4-11). One interface platter 2 is connected with the two memoryplatters 3 by cables a (4-3) and b (4—4). Cables a2 (4-10) are cablesfor access paths a2 (140) in FIG. 56 and cables b2 (4-11) are ones foraccess paths b2 (141).

This configuration produces the same effects as those of embodiments 5and 9.

In this embodiment, the shared memory units 114 are interconnected viaaccess paths a2 (140) and the cache memory units are interconnected viaaccess paths b2 (141) to make a dual system; however, instead, the samedual system effect can be obtained by writing the same data in both thetwo shared memory units 114 or both the two cache memory units 115 fromthe channel interface units 111 or the disk interface units 112. In thiscase, it is unnecessary to interconnect the shared memory units 114 orcache memory units 115 via access paths a2 (140) or access paths b2(141). However, if they are interconnected, the data in the two sharedmemory units 114 or two cache memory units can be directly cross-checkedfor confirmation or a similar purpose, resulting in improvedreliability.

The groups of shared memory units 114 and the groups of cache memoryunits 115 may be mounted as shown in FIG. 67. Concretely, the sharedmemory units 114 and cache memory units 115 are separately packaged inshared memory packages 14 and cache memory packages 15, respectively.These are mounted on one of the two areas of one memory platter dividedby a power supply boundary 300, where power is supplied to each areafrom a separate power supply. Here, the interface platters 2 areconnected to the two areas of the memory platter 3 by cables a (4-3) andb (4—4). In this case, each area of the memory platter 3 bears twoshared memory packages 14 and two cache memory packages 15 (though FIG.67 shows only one package of each memory type in each area).

Thanks to this configuration, even if a fault occurs in a shared memorypackage 14 or cache memory package 15 in one of the areas into which thememory platter 3 is divided by the power supply boundary 300, the systemcan be operated using the shared memory packages 14 or the cache memorypackages 15 mounted on the other area, so the defective shared memorypackage 14 or cache memory package 15 can be replaced without stoppingthe system.

Embodiment 11

FIGS. 6 and 7 show another embodiment of this invention.

FIG. 7 illustrates the configuration of a disk array controlleraccording to this embodiment. The disk array controller 1 has channelinterface units 111, disk interface units 112, selectors 113, sharedmemory units 114, access paths 0 (135) and access paths 1 (136).

The channel interface units 111, disk interface units 112, and sharedmemory units 114 have the same structures as those in embodiment 1.

Each selector unit 113 is connected with a total of four access paths 0(135) from two channel interface units 111 and two disk interface units112 on the basis of one path per unit. Also each selector unit 113 isconnected with two access paths 1 (36), with each path being connectedwith one of the two shared memory units 114. One such selector unit 113and two channel interface units 111 and two disk interface units 112which are connected with it constitute one group, which is hereinaftercalled a selector group 150. In this embodiment, the disk arraycontroller 1 has two selector groups 150 and two shared memory units114. Due to the above-mentioned availability of access paths, eachselector unit 113 selects two of the four requests transmitted via thefour access paths 0 (135) from the channel interface units 111 and diskinterface units 112, where the number of selected requests correspondsto the number of access paths 1 (136) to the shared memory units 114.

Here, the important thing is that the number of access paths 1 (136)from one selector unit 113 to the shared memory units 114 is smallerthan the number of access paths 0 (135) from the channel interface units111 and disk interface units 112 to one selector unit 113, and that thenumber of selector units 113 is smaller than the total number of channelinterface units and disk interface units 112. This reduces the number ofaccess paths to each shared memory unit 114, which means a decrease inthe number of cables used, leading to cost reduction and higherimplementation efficiency. In addition, the problem of LSI pin necks andpackage connector necks in the shared memory units can be resolved.

The number of channel interface units and disk interface units in aselector group 150 depends on the management unit for maintenance (thenumber of interface units subjected to each maintenance service), andother factors. One possibility is that the minimum disk array controllerconfiguration corresponds to one selector group 150.

FIG. 6 illustrates the configuration of the disk array controller 1 inthe rack-mounted form.

The channel interface units 111, disk interface units 112, selectorunits 113 and shared memory units 114 as shown in FIG. 7 are separatelypackaged in channel interface packages 11, disk interface packages 12,selector packages 13 and shared memory packages 14, respectively. Oneselector group 150 is mounted on one interface platter 2, and two sharedmemory packages 14 are mounted on a memory platter 3 different from theinterface platters 2. The interface platters 2 and memory platter 3 areconnected by cables 1 (4-2). The cables are cables for access paths 1(136) as shown in FIG. 7.

Although the selector units 113 are packaged in selector packages 13 inthis example, as shown in FIG. 8 they may be mounted on the reverse ofthe package bearing surface of the interface platters 2 withoutpackaging them in packages (the figure shows the backside). This causesno problem in implementing this embodiment and can reduce the requiredwidth of each interface platter by the amount equivalent to the width ofthe selector package 13, permitting the rack for the disk arraycontroller 1 to be more compact.

This configuration not only produces the same effects as those ofembodiment 1 but also a further effect: The use of selector units 113reduces the number of access paths to the shared memory units 114, whichmeans a decrease in the number of cables used, leading to cost reductionand higher implementation efficiency. In addition, the problem of LSIpin necks or package connector necks in shared memory units can beresolved.

Variations of this embodiment are introduced next.

FIG. 37 shows a dual cache memory system consisting of two shared memoryunits 114 connected via access path 2 (139) as in embodiment 2. FIG. 38shows the disk array controller 1 in FIG. 37 in the rack-mounted form.The two shared memory units 114 shown in FIG. 37 are separately packagedin shared memory packages 14 and the two shared memory packages 14 aremounted on different memory platters 3. The two memory platters 3 areinterconnected by cable 2 (4-9), one interface platter 2 and the twomemory platters 3 are connected by cable 1 (4-2). The cable 2 is a cablefor the access path 2 (139) shown in FIG. 37.

This configuration produces the same effects as those of embodiment 2.In this embodiment, the shared memory units 114 are interconnected viathe access path 2 (139) to make a dual system; however, instead, thesame dual system effect can be obtained by writing the same data in boththe two shared memory units 114 from the channel interface units 111,disk interface units 112 or selector units 113. In this case, it isunnecessary to interconnect the shared memory units 114 via the accesspath 2 (139). However, if they are interconnected via the access path 2(139), the data in the two shared memory units 114 can be directlycross-checked for confirmation or a similar purpose, resulting inimproved reliability.

Again, in this case, as shown in FIG. 40, the selector units 113 may bemounted on the reverse of the package bearing surface of the interfaceplatters 2 (the figure shows the backside).

A dual shared memory system can be realized by arranging two sharedmemory units 114 as shown in FIG. 47. Concretely, two shared memoryunits 114 are separately packaged in shared memory package and the twopackages are mounted on two areas of a memory platter 3 divided by apower supply boundary 300 as in embodiment 3.

This configuration produces the same effects as those of embodiment 3.

Again, in this case, as shown in FIG. 49, the selector units 113 may bemounted on the reverse of the package bearing surface of the interfaceplatters 2 (the figure shows the backside of the platters).

FIG. 23 shows a variation of this embodiment in which cache memory units115 for storing data to be recorded in magnetic disk drives 120, andshared memory units 114 storing control data for the cache memory units115 and disk array controller 1 are physically divided, selectors (CMselector units 123) connected to the cache memory units 115 andselectors (SM selector units 113) connected to the shared memory units114 are physically independent of each other and access paths a0 (131)and access paths a1 (132) to the shared memory units 114, and accesspaths b0 (133) and access paths b1 (134) to the cache memory units 115are independent of each other.

FIG. 24 illustrates the configuration of the disk array controller 1 inFIG. 23 in the rack-mounted form. Here, the SM selector units 113 and CMselector units 123 are separately packaged in SM selector packages 13and CM selector packages 23, respectively. The cache memory units 115and shared memory units 114 are separately packaged in cache memory unitpackages 15 and shared memory packages 14, respectively, which aremounted on a memory platter 3. As shown in FIG. 24, in place of thecable 1 (4-2) which connects each interface platter 2 and the memoryplatter 3 in FIG. 6, cable a1 (4-7) for access path a1 (132) to theshared memory units 114 and cable b1 (4-8) for access path b1 (134) tothe cache memory units 115 are used.

Since in this configuration, the access paths from the channel interfacepackages 11 and disk interface packages 12 to the cache memory packages15 or shared memory packages 14 are physically independent, it ispossible to distinguish between faults related to access to the cachememory units 115 (faults in the cache memory units 115, or the CMselector units 123, access paths b0 (133), access paths b1 or others foraccess to them) and faults related to access to the shared memory units114 (faults in the shared memory units 114 or the SM selector units 113,access paths a0 (131), access paths a1 (132) or others for access tothem) so that defective parts can be independently repaired withoutaffecting other parts.

Again, in this case, as shown in FIG. 26, the SM selector units 113 andCM selector units 123 may be mounted on the reverse of the packagebearing surface of the interface platters 2 (the figure shows thebackside of the platters)

FIG. 59 shows a variation of this embodiment in which two shared memoryunits 114 are interconnected via access path a2 (140) and two cachememory units 115 are interconnected via access path b2 (141) to make adual system.

FIG. 60 illustrates the configuration of the disk array controller 1 inFIG. 59 in the rack-mounted form. As shown in FIG. 59, like embodiment5, two shared memory units 114 and two cache memory units 115 areseparately packaged in shared memory packages 14 and cache memorypackages 15, respectively, and one shared memory package 14 and onecache memory package 15 are mounted on one memory platter 3, with thetwo memory platters 3 being interconnected by cable a2 (4-10) and cableb2 (4-11). One interface platter 2 is connected to the two memoryplatters 3 by cable a1 (4-7) and cable b1 (4-8). The cable a2 (4-10) andcable b2 (4-11) are cables for the access path a2 (140) and access pathb2 (141) shown in FIG. 59, respectively.

This configuration produces the same effects as those of embodiment 5.

As shown in FIGS. 59 and 60, the shared memory units 114 areinterconnected via access path a2 (140) and the cache memory units 115interconnected via access path b2 (141) to make a dual system; however,instead, the same dual system effect can be obtained by writing the samedata in both the two shared memory units 114 or both the two cachememory units 115 from the channel interface units 111, disk interfaceunits 112, SM selector units 113 or CM selector units 123. In this case,it is unnecessary to interconnect the shared memory units 114 via accesspath a2 (140) or the cache memory units 15 via access path b2. However,if they are interconnected via access path a2 (140) or access path b2(141), the data in the two shared memory units 114 or the two cachememory units 115 can be directly cross-checked for confirmation or asimilar purpose, resulting in improved reliability.

Again, in this case, as shown in FIG. 62, the SM selector units 113 andthe CM selector units 123 may be mounted on the reverse of the packagebearing surface of the interface platters 2 (the figure shows thebackside of the platters)

FIG. 69 is a variation of this embodiment in which two shared memoryunits 114 and two cache memory units 115 are mounted in the same way asin embodiment 6. In other words, they are separately packaged in sharedmemory packages 14 and cache memory packages 15, respectively, which aremounted on one memory platter 3 which is divided into two areas by apower supply boundary 300.

This configuration produces the same effects as those of embodiment 6.

Again, in this case, as shown in FIG. 71, the SM selector units 113 andCM selector units 123 may be mounted on the reverse of the packagebearing surface of the interface platters 2 (the figure shows thebackside of the platters).

Embodiment 12

FIGS. 9 and 10 show another embodiment of this invention.

FIG. 10 shows the configuration of a disk array controller according tothis invention. The disk array controller 1 has channel interface units111, disk interface units 112, selector units 113, shared memory units114, access paths 0 (135) and access paths 1 (136). It is basically thesame in structure as in embodiment 11.

The difference is as follows. In this embodiment, each of the channelinterface units 111 and disk interface units 112 has two access paths 0(135), and one of the paths is connected to the selector unit 113 in theselector group 150 it belongs to, and the other path connected to theselector unit 113 in the other selector group 150. Therefore, there aretwo routes for access to the shared memory units 114 from each of thechannel interface units 111 or disk interface units 112. Usually the twoaccess routes are used to share the load in a balanced way so that ifone access route becomes ineffective due to a fault or other reason, theother access route can be used to operate the system uninterruptedly. Apair of selector groups which each have access paths to the selector inthe other group in this way is hereinafter called a redundant system155.

One selector unit 113 has a total of eight access paths 0 (135) on thebasis of one path per unit: paths from the two channel interface units111 and two disk interface units 112 within the group it belongs, aswell as paths from the two channel interface units 111 and two diskinterface units 112 within the other group. Also each selector unit 113has a total of four access paths 1 (136) to the two shared memory units,where each shared memory unit has two access paths. Due to theabove-mentioned availability of access paths, each selector unit 113selects four of the eight requests transmitted via the eight accesspaths 0 (135) from the channel interface units 111 and disk interfaceunits 112, where the number of selected requests corresponds to thenumber of access paths 1 (136) to the shared memory units 114. In thisembodiment, the disk array controller 1 has one redundant system 155 andtwo shared memory units.

Here, the important thing is that the number of access paths 1 (136)from one selector unit 113 to the shared memory units 114 is smallerthan the number of access paths 0 (135) from the channel interface units111 and disk interface units 112 to one selector unit 113, and that thenumber of selector units 113 is smaller than the total number of channelinterface units 111 and disk interface units 112. This reduces thenumber of access paths to each shared memory unit 114, which means adecrease in the number of cables used, leading to cost reduction. Inaddition, the problem of LSI pin necks or package connector necks inshared memory units can be resolved.

The number of channel interface units and the number of disk interfaceunits within a selector group 150 depends on the management unit formaintenance (the number of interface units subjected to each maintenanceservice), and other factors. One possibility is that, on the assumptionthat the minimum disk array controller configuration constitutes oneredundant system 155, a plurality of such redundant systems areprovided.

FIG. 9 illustrates the configuration of the disk array controller 1 inthe rack-mounted form. The channel interface units 111, disk interfaceunits 112, selector units 113 and shared memory units 114 as shown inFIG. 10 are separately packaged in channel interface packages 11, diskinterface packages 12, selector packages 13 and shared memory packages14, respectively. One selector group 150, which consists of one selectorpackage 13 and channel interface packages 11 and disk interface packages12 connected with it, is mounted on one interface platter 2 and the twoshared memory packages 14 are mounted on a memory platter 3 differentfrom the interface platters 2. Each interface platter 2 and the memoryplatter 3 are connected by cable 1 (4-2). This cable is a cable for theaccess path 1 (136) which connects a selector unit 113 and a sharedmemory unit 114 as shown in FIG. 10. The two interface platters whichconstitute a redundant system are interconnected by cable 0 (4-1). Thiscable is a cable for the access paths 0 (135) which connect the channelinterface units 111 and disk interface units 112 within one selectorgroup 150 and the selector unit 113 within the other selector group.

Here, when two cables 0 (4-1) are used instead of one and one of them isused for access path 0 (135) to connect the interface units within oneselector group 150 with the selector unit 113 within the other group150, and the other cable is used for access path 0 (135) to connect theselector unit 113 within the former selector group 150 with theinterface units within the latter selector group 150, even if one of theaccess paths 0 (135) fails, the cable 0 (4-1) concerned can be replacedwithout affecting the other access path 0 (135).

Although the selector units 113 are packaged in selector packages inthis example, they may also be directly mounted on the reverse of thepackage bearing surface of the interface platters 2, as shown in FIG. 8,without packaging them in packages (the figure shows the back side ofthe platters).

When, as mentioned above, the access paths of each interface package areconnected not only with the selector package 13 on the same interfaceplatter 2 on which it is mounted, but also with the selector package 13on the other interface platter 2 in the same redundant system, even ifthe selector package 13 on one of the interface platters 2 fails, theinterface packages mounted on the same interface platter 2 bearing thedefective selector package 13 can access the shared memory units 114through the selector unit 113 on the other interface platter 2 and thusthe defective selector package 113 can be replaced without stopping theinterface units in the selector group 150 to which the defectiveselector unit 113 belongs. This reduces the number of system componentswhich should be stopped in case of faults.

Variations of this embodiment are introduced below.

In these variations, the selector units 113 may be mounted on thereverse of the package bearing surface of the interface platters 2 (thefigures concerned show the backside of the platters).

FIG. 42 illustrates a variation of this embodiment in which the twoshared memory units 114 are interconnected via access path 2 (139) tomake a dual system as in embodiment 2.

FIG. 43 illustrates the configuration of the disk array controller 1 inFIG. 42 in the rack-mounted form. Two shared memory units 114 areseparately packaged in shared memory packages 14, which are mounted ondifferent memory platters 3. The memory platters 3 are interconnected bycable 2 (4-9) and one interface platter 2 and the two memory platters 3are connected by cable 1 (4-2). The cable 2 (4-9) is a cable for theaccess path 2 (139) as shown in FIG. 42.

This produces the same effects as those of embodiment 2.

In this variation, the shared memory units 114 are interconnected viaaccess paths 2 (139) to make a dual system; however, instead, the samedual system effect can be obtained by writing the same data in both thetwo shared memory units 114 from the channel interface units 111, diskinterface units 112 or selector units 113. In this case, it isunnecessary to interconnect the shared memory units 114 via access path2 (139). However, if they are interconnected via access path 2 (139),the data in the two shared memory units 114 can be directlycross-checked for confirmation or a similar purpose, resulting inimproved reliability.

FIG. 51 shows another variation in which two shared memory units 114make up a dual system. Like embodiment 3, two shared memory units 114are separately packaged in shared memory packages 14, which are mountedon two areas of one memory platter 3 divided by a power supply boundary300.

This produces the same effects as those of embodiment 3.

FIG. 28 illustrates a variation of this embodiment in which cache memoryunits 115 for storing data to be recorded in magnetic disk drives 120,and shared memory units 114 for storing control data for the cachememory units 115 and the disk array controller 1 are physicallyindependent of each other, selectors (CM selector units 123) connectedto the cache memory units 115 and selectors (SM selector units 113)connected to the shared memory units 114 are physically independent ofeach other, and access paths a0 (131) and access paths a1 (132) to theshared memory units 114, and access paths b0 (133) and access paths b1(134) to the cache memory units 115 are independent of each other.

FIG. 29 illustrates the configuration of the disk array controller 1 inFIG. 28 in the rack-mounted form. Here, the SM selector units 113 and CMselector units 123 are separately packaged in SM selector packages 13and CM selector packages 23, respectively. The cache memory units 115and shared memory units 114 are separately packaged in cache memory unitpackages 15 and shared memory packages 14, respectively, which aremounted on a memory platter 3. In place of the cable 1 (4-2) whichconnects each interface platter 2 and the memory platter 3 in FIG. 9,cable a1 (4-7) for access path a1 (132) to the shared memory units 114and cable b1 (4-8) for access path b1 (134) to the cache memory units115 are used as shown in FIG. 29. Also, in place of the cable 0 (4-1)which interconnects the interface platters 2, cable a0 (4-5) for accesspath a0 (131) to the shared memory units 114 and cable b0 (4-6) foraccess path b0 (133) to the cache memory units 115 are used.

Since in this configuration, the access paths from the channel interfacepackages 11 and disk interface packages 12 to the cache memory packages15 or shared memory packages 14 are physically independent, it ispossible to distinguish between faults related to access to the cachememory units 115 (faults in the cache memory units 115, or the CMselector units 123, access paths b0 (133), access paths b1 (134) orothers for access to them) and faults related to access to the sharedmemory units 114 (faults in the shared memory units 114 or the SMselector units 113, access paths a0 (131), access paths a1 (132) orothers for access to them) so that defective parts can be independentlyrepaired without affecting other parts.

FIG. 64 shows a variation of this embodiment in which two shared memoryunits 114 are interconnected via access path a2 (140) and two cachememory units 115 are interconnected embodiment 5. FIG. 65 illustratesthe configuration of the disk array controller 1 in FIG. 64 in therack-mounted form. As shown in FIG. 65, two shared memory units 114 andtwo cache memory units 115 are separately packaged in shared memorypackages 14 and cache memory packages 15, respectively, and one sharedmemory package 14 and one cache memory package 15 are mounted on onememory platter 3, with the two memory platters 3 being connected bycable a2 (4-10) and cable b2 (4-11). The interface platters 2 and memoryplatters 3 are connected by cables a1 (4-7) and cables b1 (4-8). Thecable a2 (4-10) and cable b2 (4-11) are cables for access path a2 (140)and access path b2 (141), respectively.

This produces the same effects as those of embodiment 5. In thisvariation, the shared memory units 114 are interconnected via accesspath a2 (140) and the cache memory units 115 are interconnected viaaccess path b2 (141) to make a dual system; however, instead, the samedual system effect can be obtained by writing the same data in both thetwo shared memory units 114 or both the two cache memory units 115 fromthe channel interface units 111, disk interface units 112 or SM selectorunits 113 or CM selector units 123. In this case, it is unnecessary tointerconnect the shared memory units 114 or the cache memory units 115via access path a2 (140) or access path b2 (141). However, if they areinterconnected via access path a2 (140) or access path b2 (141), thedata in the two shared memory units 114 or the two cache memory units115 can be directly cross-checked for confirmation or a similar purpose,resulting in improved reliability.

FIG. 73 shows a variation of this embodiment in which two shared memoryunits 114 and two cache memory units 115 are separately packaged inshared memory packages 14 and cache memory packages 15, respectively,which are mounted on one memory platter 3 which is divided into twoareas by a power supply boundary 300 as in embodiment 6.

This produces the same effects as those of embodiment 6.

Embodiment 13

FIG. 11 shows another embodiment of this invention.

FIG. 11 illustrates one implementation of the disk array controller 1shown in FIG. 4 for embodiment 1 in the rack-mounted form. The channelinterface units 111, disk interface units 112 and shared memory units114 as shown in FIG. 4 are separately packaged in channel interfacepackages 11, disk interface packages 12, and shared memory packages 14,respectively. Two channel interface packages 11, two disk interfacepackages 12 and one shared memory package 14, which constitute a groupcalled a cluster (165, 166), are mounted on one interface platter 2.

Therefore, the configuration of this embodiment differs from that ofembodiment 1 in FIG. 1 in that a shared memory package 14 is mounted onan interface platter 2 together with channel interface packages 11 anddisk interface packages 12.

This embodiment has two clusters, cluster 0 (165) and cluster 1 (166).However, the numbers of clusters, and the number of channel interfaceunits, disk interface units and shared memory units 113 in one clusterare not limited as of above. These numbers depend on the minimum ormaximum system configuration of the disk array controller, and theminimum unit of system expansion. In other words, they depend onperformance, cost, scalability and other requirements. One possibilityis that one cluster is made up of a minimum disk array controllerconfiguration.

In adding an interface platter 2, the new interface platter 2 and theexisting interface platters 2 are connected by two cables 4. Thesecables 4 are cables for the access paths 0 (135) (shown in FIG. 4) whichconnect the channel interface units 111 or disk interface units 112within one cluster, with the shared memory unit 114 within the othercluster.

Although each of the two clusters contains a shared memory package 14 inthis example, it is also acceptable that one cluster contains all theshared memory packages 14 used in the disk array controller 1 while theother cluster has no shared memory package 14. This can reduce thenumber of cluster interconnection cables 4 shown in FIG. 11 to one,which leads to cost reduction.

The disk array controller in this embodiment uses a smaller number ofcables than that in embodiment 1, leading to cost reduction and higherimplementation efficiency.

FIGS. 33, 46, 19, 55 and 68 illustrate variations of this embodiment.These show other configurations of the disk array controller detailed inthe description of embodiments 2 to 6. They are different from theconfiguration of the disk array controller in embodiments 2 to 6 simplyin that a shared memory package 14 is mounted on an interface platter 2together with channel interface packages 11 and disk interface packages12. They will be briefly outlined below. Needless to say, they producethe same effects as those of embodiments 2 to 6.

FIG. 33 shows one implementation of the disk array controller 1 shown inFIG. 31 for embodiment 2. The configuration in FIG. 33 differs from thatin FIG. 32 for embodiment 2 in that one cluster contains one sharedmemory package 14.

FIG. 46 shows a variation of the configuration shown in FIG. 45 forembodiment 3. Two pairs of shared memory packages 14 are mounted ondifferent interface platters 2. Each of the interface platters isdivided by a power supply boundary 300 into two areas, to which power isseparately supplied from two power supplies. Each shared memory package14 in one pair is mounted in one of the areas to which power is suppliedfrom different power supplies.

FIG. 19 illustrates one implementation of the disk array controller 1shown in FIG. 17 for embodiment 4. FIG. 19 is different from FIG. 18 forembodiment 4 only in that a cluster contains one shared memory package14 and one cache memory package 15.

FIG. 55 illustrates one implementation of the disk array controller 1shown in FIG. 53 for embodiment 5. FIG. 55 is different from FIG. 54 forembodiment 5 only in that a cluster contains one shared memory package14 and one cache memory package 15.

FIG. 68 shows a variation of the implementation shown in FIG. 67 forembodiment 6. Each of the interface platters is divided by a powersupply boundary 300 into two areas, to which power is separatelysupplied from two power supplies. One shared memory package 14 and onecache memory package 15 are mounted in one of these areas energized bydifferent power supplies.

Embodiment 14

FIG. 12 shows another embodiment of this invention.

FIG. 12 shows the configuration of another disk array controlleraccording to this invention. The disk array controller 1 has thefollowing: channel interface units 111; disk interface units 112; sharedmemory units 114; two shared buses 0 (31) which connect them; shared businterconnect controllers 140 for connection of the shared buses 0 (31)from different clusters; and access paths 0 (135). The relationshipamong the channel interface units 111, disk interface units 112 andshared memory units 114 is the same as in embodiment 7.

In this embodiment, two channel interface units 111, two disk interfaceunits 112, one shared memory unit 114, two shared buses 0 (31) and twoshared bus interconnect controllers 140 constitute one group, which ishere called a cluster. In this embodiment, the disk array controllershas two clusters (165, 166).

The shared bus interconnect controllers 140 work as follows to connectshared buses from different clusters.

For access from a channel interface unit 111 or disk interface unit 112within one cluster to the shared memory 114 in the other cluster, the SMaccess circuit (not shown here) inside the channel interface unit 111 ordisk interface unit 112 obtains the right to use the shared buses 0 (31)and then accesses a shared bus interconnect controller 140 connectedwith the shared buses 0 (31) to issue a request for access to the sharedmemory unit 114 within the other cluster. That shared bus interconnectcontroller 140 sends the access request to a shared bus interconnectcontroller 140 connected with the shared buses 0 (31) within the othercluster. After obtainment of the right to use the shared buses 0 (31),the shared bus interconnect controller connected with the shared buses 0(31) within the other cluster sends the access request to the sharedmemory unit.

For connection of the clusters, the shared memory units 114 may beinterconnected via access paths 0 (135) as shown in FIG. 13. The diskarray controller 1 operates as each of the channel interface units 111and disk interface units 112 accesses the shared memory units; so, byinterconnecting the shared memory units 114 as mentioned above, thechannel interface units 111 and disk interface units 112 can each accessthe shared memory units 114.

Needless to say, the number of clusters is not limited as above.

One shared bus 0 (31) may be used instead of two. However, the use oftwo shared buses makes the access paths to the shared memory units 114redundant, resulting in improved trouble resistance.

FIG. 11 shows the configuration of the disk array controller 1 in FIG.12 or 13 in the rack-mounted form. The channel interface units 111, diskinterface units 112 and shared memory units 114 as shown in FIG. 12 or13 are separately packaged in channel interface packages 11, diskinterface packages 12 and shared memory packages 14, respectively.Channel interface packages 11, disk interface packages 12 and a sharedmemory package 14, all of which constitute one cluster, are mounted onone interface platter 2. Shared buses 0 (31) are wired on the interfaceplatter 2 and shared bus interconnect controllers 140 are directlymounted thereon (these are not shown in the figure). In theconfiguration in FIG. 13, the shared buses are wired on the interfaceplatter 2 but the shared bus interconnect controllers 140 are notmounted thereon.

In adding an interface platter 2, the new interface platter 2 and theexisting interface platters 2 are connected by two cables 4. In case ofthe disk array controller 1 in FIG. 12, these cables correspond tocables for the access paths 0 (135) which connect shared businterconnect controllers 140 within one cluster, with those within theother cluster, while, in case of the disk array controller 1 in FIG. 13,they are cables for the access paths 0 (135) which connect the sharedmemory unit 114 within one cluster with that in the other cluster.

This configuration not only produces the same effects as those ofembodiment 7 but also a further effect: Since each cluster contains ashared memory unit 114, this disk array controller is less scalable thanthat in embodiment 7 but the number of cables used can be decreased,leading to cost reduction and higher implementation efficiency.

Variations of this embodiment are introduced below.

FIG. 35 shows a variation of this embodiment in which, in the disk arraycontroller 1 in FIG. 12, two shared memory units 114 are interconnectedvia access path 2 (139) to make a dual system as in embodiment 2. FIG.33 illustrates the configuration of the disk array controller 1 in FIG.35 in the rack-mounted form. Two shared memory units 114 are separatelypackaged in shared memory packages 14, which are mounted on differentinterface platters 2. The interface platters 2 are interconnected bycable 2 (4-9). The cable 2 (4-9) is a cable for access path 2 (139). Incase of the disk array controller 1 in FIG. 13, the same dual systemeffect can be obtained by connecting the shared memory unit 114 withinone cluster with that within the other cluster via access path 2 (139)as shown in FIG. 36.

It is also possible that one access path serves as both access path 0(135) for access from a channel interface unit 111 or disk interfaceunit 112 within one cluster to the shared memory unit 114 within theother cluster, and the access path 2 (139) to make a dual system. Itmust be noted that the throughput of such an access path should behigher than the sum of the throughput of the access paths 0 (135) andthat of the access path 2 (139); otherwise, the overall throughput ofthe disk array controller 1 would deteriorate.

This produces the same effects as those of embodiment 2.

Another possible approach to making a dual system is that one clustercontains two interconnected shared memory units 114 instead ofinterconnecting two shared memory units 114 of different clusters.

FIG. 46 shows a variation in which a shared memory unit 114 is added toone cluster and the two shared memory units 114 in the cluster areseparately packaged in shared memory packages 14, which are mounted onthe two areas of the interface platter 2 divided by a power supplyboundary 300 as in embodiment 3.

This produces the same effects as those of embodiment 3.

FIG. 21 shows a variation of the disk array controller 1 in FIG. 12 inwhich the cache memory units 115 for storing data to be recorded inmagnetic disk drives 120 and the shared memory units 114 for storingcontrol data for the cache memory units 115 and disk array controller 1are physically independent as in embodiment 4. Here, the shared buses 0(31) shown in FIG. 12 are divided into shared buses b0 (35) fortransmitting data from the magnetic disk drives 120 and shared buses a0(33) for transmitting control data for the cache memory units 115 anddisk array controller 1, and the channel interface units 111 and diskinterface units 112 are connected to both the shared buses a0 (33) andshared buses b0 (35). Further, the cache memory units 115 and sharedmemory units 114 are connected to the shared buses b0 (35) fortransmitting data from the magnetic disk drives 120 and shared buses a0(33) for transmitting control data for the disk array controller 1,respectively. Connections are made between the shared buses a0 (33) ofthe different clusters and between the shared buses b0 (35) of thedifferent clusters through shared bus interconnect controllers 140, viaaccess paths a (137) and access paths b (138), respectively. As avariation of the disk array controller 1 in FIG. 13, as shown in FIG.22, connections are made between the shared memory units 114 of thedifferent clusters and between the cache memory units 115 of thedifferent clusters via access paths a (137) and access paths b (138),respectively.

FIG. 19 shows the configuration of the disk array controller 1 in FIG.21 or FIG. 22 in the rack-mounted form. The cache memory units 115 andshared memory units 114 are separately packaged in cache memory packages15 and shared memory packages 14, respectively, which are mounted on aninterface platter 2. The cables 4 shown in FIG. 11 which interconnectinterface platters 2 are divided into cables a (4-3) for access paths a(137) for connection between shared buses a0 (33) and cables b (4—4) foraccess paths b (138) for connection between shared buses b0 (35) asshown in FIG. 19.

This produces the same effects as those of embodiment 4.

FIG. 57 shows a variation of the disk array controller 1 in FIG. 12 inwhich the two shared memory units 114 are interconnected via access patha2 (140) and the two cache memory units 115 are interconnected viaaccess path b2 (141) as in embodiment 5. As a variation of the diskarray controller 1 in FIG. 13, access path a2 (140) and access path b2(141) for a dual system should be provided as shown in FIG. 58. It isalso possible that one access path serves as both access path a0 (131)for access from a channel interface unit 111 or disk interface unit 112within one cluster to the shared memory unit 114 within the othercluster, and the access path a2 (140) to make a dual system. It is alsopossible that one access path serves as both access path b0 (133) foraccess from a channel interface unit 111 or disk interface unit 112within one cluster to the cache memory unit 115 within the othercluster, and the access path b2 (141) to make a dual system. In thatcase, it must be noted that the throughput of such an access path forthe shared memory units should be higher than the sum of the throughputof the access path a0 (131) and that of the access path a2 (140), andthe throughput of such an access path for the cache memory units shouldbe higher than the sum of the throughput of the access path b0 (133) andthat of the access path b2 (141); otherwise, the overall throughput ofthe disk array controller 1 would deteriorate.

FIG. 55 shows the configuration of the disk array controller 1 in FIG.57 or FIG. 58 in the rack-mounted form. The shared memory units 114 andcache memory units 115 are separately packaged in shared memory packages14 and cache memory packages 15, respectively, which are mounted ondifferent interface platters 2, with the interface platters 2 beinginterconnected by cable a2 (4-10) and cable b2 (4-11). The cable a2(4-10) is a cable for the access path a2 (140) and the cable b2 (4-11)is a cable for the access path b2 (141).

This produces the same effects as those of embodiment 5.

Another possible approach to making a dual system is that one clustercontains two interconnected shared memory units 114 and twointerconnected cache memory units 115 instead of interconnecting twoshared memory units 114 and two cache memory units 115 of differentclusters as in FIGS. 57 and 58.

FIG. 68 shows a variation which uses two pairs of interconnected sharedmemory packages 14 and two pairs of interconnected cache memory packages15, where one shared memory package and one cache memory package aremounted on each of the two areas of the interface platter 2 divided by apower supply boundary 300 as in embodiment 6.

This produces the same effects as those of embodiment 6.

Embodiment 15

FIG. 14 shows another embodiment of this invention.

FIG. 14 shows one configuration of the disk array controller 1 shown inFIG. 7 for embodiment 11 in the rack-mounted form. A selector group 150,which consists of one selector package 13, and channel interfacepackages 11 and disk interface packages 12 which are connected with it,and one shared memory package 14 are mounted on one interface platter 2.All these on the platter constitute one cluster as defined earlier.

In adding an interface platter 2, the new interface platter 2 and theexisting interface platters 2 are connected by two cables 1 (4-2). Thesecables 1 (4-2) are cables for the access paths 1 (136) which connect theselector unit 113 within one cluster, with the shared memory unit 114within the other cluster. In short, the configuration of this embodimentis different from the configuration of embodiment 11 shown in FIG. 6 inthat each shared memory package is mounted on an interface platter 2.

Although the selector units 113 are mounted in selector packages 13 inthis example, they may be directly mounted on the reverse of the packagebearing surface of the interface platters 2 without packaging them inpackages as shown in FIG. 15 (the figure shows the backside of theplatters). This reduces the required width of each interface platter 2by the amount equivalent to the width of the selector package 13,permitting the rack for the disk array controller 1 to be more compact.

Although each of the two clusters contains a shared memory package 14 inthis example, it is also acceptable that one cluster contains all theshared memory packages 14 used in the disk array controller 1 while theother cluster has no shared memory package 14. This can decrease thenumber of cluster interconnection cables 1 (4-2) shown in FIG. 14 toone, which leads to cost reduction.

This configuration not only produces the same effects as those ofembodiment 11 but also a further effect: Since each cluster contains ashared memory unit 114, this disk array controller is less scalable thanthat of embodiment 11 but the number of cables used can be decreased,leading to cost reduction and higher implementation efficiency.

Variations of this embodiment are introduced below. These variations aredifferent from the variations of embodiment 11 only in that sharedmemory packages 14 are mounted on interface platters 2; they are brieflyoutlined next.

In these variations, it is also acceptable that the selector packages113 are directly mounted on the reverse of the package bearing surfaceof the interface platters 2, without packaging them in packages (thefigure shows the backside of the platters).

FIG. 39 illustrates a configuration in the rack-mounted form of the diskarray controller 1 of embodiment 11 in FIG. 37. In this variation, twoshared memory units 114 are interconnected in the same way as inembodiment 2.

This produces the same effects as those of embodiment 2.

In this variation, the shared memory units 114 are interconnected viaaccess path 2 (139) to make a dual system; however, instead, the samedual system effect can be obtained by writing the same data in both theshared memory units 114 from the channel interface units 111, diskinterface units 112 or selector units 113. In this case, it isunnecessary to interconnect the shared memory units 114 via access path2 (139). However, if they are interconnected via access path 2 (139),the data in the two shared memory units 114 can be directlycross-checked for confirmation or a similar purpose, resulting inimproved reliability.

FIG. 48 shows a variation in which a shared memory unit 114 is added toone cluster and the two shared memory units 114 in the cluster areseparately packaged in shared memory packages 14, which are mounted onthe two areas of the interface platter 2 divided by a power supplyboundary 300 as in embodiment 3.

This produces the same effects as those of embodiment 3.

Although each of the two clusters contains shared memory packages 14 inthis example, it is also acceptable that one cluster contains all theshared memory packages 14 used in the disk array controller 1 while theother cluster has no shared memory packages 14. This can decrease thenumber of cluster interconnection cables 1 (4-2) in FIG. 48 to one,which leads to cost reduction and higher implementation efficiency.

FIG. 23 shows a variation in which, as in embodiment 4, each sharedmemory unit 114 of the disk array controller 1 in FIG. 7 is physicallydivided into a cache memory unit 115 for storing data to be recorded inmagnetic disk drives 120, and a shared memory unit 114 for storingcontrol data for the cache memory unit 115 and disk array controller 1.Selectors (CM selector units 123) connected to the cache memory units115, and selectors (SM selector units 113) connected to the sharedmemory units 114 are physically independent, and access paths a0 (131)and access paths a1 (132) to the shared memory units 114, and accesspaths b0 (133) and access paths b1 (134) to the cache memory units 115,are independent of each other.

This produces the same effects as those of embodiment 4.

Although each of the two clusters contains a shared memory package 14and a cache memory package 15 in this example, it is also acceptablethat one cluster contains all the shared memory packages 14 and cachememory packages 15 used in the disk array controller 1 while the othercluster has no shared memory package 14 nor cache memory package 15.This can decrease the number of cluster interconnection cables a1 (4-7)and the number of cables b1 (4-8) shown in FIG. 25 to one, which leadsto cost reduction.

FIG. 59 shows a variation in which two shared memory units 114 areinterconnected via access path a2 (140) and two cache memory units 115are interconnected via access path b2 (141) to make a dual system.

FIG. 61 shows the configuration of the disk array controller 1 in FIG.59 in the rack-mounted form. One shared memory package 14 and one cachememory package 15 are mounted on an interface platter 2, with theinterface platters 2 being interconnected by cable a2 (4-10) and cableb2 (4-11). The cable a2 (4-10) is a cable for the access path a2 (140)and the cable b2 (4-11) is a cable for the access path b2 (141).

This produces the same effects as those of embodiment 5.

In this variation, the shared memory units 114 are interconnected viaaccess path a2 (140) and the cache memory units 115 via access path b2(141) to make a dual system; however, instead, the same dual systemeffect can be obtained by writing the same data in both the sharedmemory units 114 or both the cache memory units 115 from the channelinterface units 111, disk interface units 112 or SM selector units 113or CM selector units 123. In this case, it is unnecessary tointerconnect the shared memory units 114 via access path a2 (140) or thecache memory units 115 via access path b2 (141). However, if they areinterconnected via access path a2 (140) or b2 (141), the data in the twoshared memory units 114 or two cache memory units 115 can be directlycross-checked for confirmation or a similar purpose, resulting inimproved reliability.

FIG. 70 shows a variation in which two shared memory packages 14 and twocache memory packages 15 are contained in one cluster instead of onememory package 14 and one cache memory package 15 in each of theclusters shown in FIG. 59, where one set which consists of one sharedmemory package 14 and one cache memory package 15 is mounted on each ofthe two areas of the interface platter 2 divided by a power supplyboundary 300.

This produces the same effects as those of embodiment 6.

It is also acceptable that one cluster contains all the shared memorypackages 14 and cache memory packages used in the disk array controller1 while the other cluster has no shared memory package 14 nor cachememory package 15. This can decrease the number of clusterinterconnection cables a1 (4-7) and the number of cables b1 (4-8) shownin FIG. 70 to one, which leads to cost reduction.

Embodiment 16

FIG. 16 shows another embodiment of this invention.

FIG. 16 illustrates one configuration in the rack-mounted form of thedisk array controller 1 of embodiment 12 shown in FIG. 10. Thisconfiguration is different from that of embodiment 12 in FIG. 9 in thatthe shared memory units in FIG. 10 are contained in clusters.

In this configuration, as compared to the configuration in FIG. 9, thenumber of access paths 1 (136) which connect the selector units (113)and shared memory units 114 can be decreased, which decreases the numberof cables used in the disk array controller housed in the rack, leadingto cost reduction.

Although the selector units 113 are packaged in selector packages 13 inthis example, they may be directly mounted on the reverse of the packagebearing surface of the interface platters 2 without packaging them inpackages (the figure shows the backside of the platters). This reducesthe required width of each interface platter 2 by the amount equivalentto the width of the selector package 13, permitting the rack for thedisk array controller 1 to be more compact.

Although each of the two clusters contains a shared memory package 14 inthis example, it is also acceptable that one cluster contains all theshared memory packages 14 used in the disk array controller 1 while theother cluster has no shared memory package 14. This can decrease thenumber of cluster interconnection cables 1 (4-2) shown in FIG. 16 toone, which leads to cost reduction.

Variations of this embodiment are introduced below. These variations aredifferent from the variations of embodiment 12 only in that sharedmemory units 114 are contained in clusters; they are briefly outlinednext.

Again, by mounting the selector units 113 directly on the reverse of thepackage bearing surface of the interface platters 2 (the figure showsthe backside of the platters), the required width of each interfaceplatter 2 can be reduced, permitting the rack for the disk arraycontroller 1 to be more compact.

FIG. 44 shows a variation of the disk array controller 1 in FIG. 42, inwhich two shared memory units 114 are separately packaged in sharedmemory packages 14, which are mounted on different interface platters 2.

Also, the same dual system effect can be obtained by writing the samedata in both the shared memory units 114 from the channel interfaceunits 111, disk interface units 112 or selector units 113. In this case,it is unnecessary to interconnect the shared memory units 114 via accesspath 2 (139). However, if they are interconnected via access path 2(139), the data in the two shared memory units 114 can be directlycross-checked for confirmation or a similar purpose, resulting inimproved reliability.

FIG. 52 shows a variation of the configuration in FIG. 42 in which onecluster contains two shared memory packages 14 instead of one, where oneshared memory package 14 in a dual system is mounted on each of the twoareas of each interface platter 2 divided by a power supply boundary 300as in embodiment 3.

Although each of the two clusters contains shared memory packages 14 inthis example, it is also acceptable that one of the two clusterscontains all the shared memory packages 14 used in the disk arraycontroller 1 while the other cluster has no shared memory packages 14.

FIG. 30 illustrates a variation in which, as in embodiment 4, eachshared memory unit 114 is physically divided into a cache memory unit115 for storing data to be recorded in magnetic disk drives 120, and ashared memory unit 114 for storing control data for the cache memoryunit 115 and the disk array controller 1.

Since in this configuration, the access paths from the channel interfacepackages 11 and disk interface packages 12 to the cache memory packages15 or shared memory packages 14 are physically independent, it ispossible to distinguish between two types of faults, faults related toaccess to the cache memory units 115 (faults in the cache memory units115, or the CM selector units 123, access paths b0 (133), access pathsb1 (134) or others for access to them) and faults related to access tothe shared memory units 114 (faults in the shared memory units 114 orthe SM selector units 113, access paths a0 (131), access paths a1 orothers for access to them) so that defective parts can be independentlyrepaired without affecting other parts.

Although each of the two clusters contains a shared memory package 14and a cache memory package 15 in this example, it is also acceptablethat one cluster contains all the shared memory packages 14 and cachememory packages 15 used in the disk array controller 1 while the othercluster has no shared memory package 14 nor cache memory package 15.

FIG. 66 shows a variation in which two shared memory units 114 areinterconnected via access path a2 (140) and two cache memory units 115via access path b2 (141) as in embodiment 5.

This produces the same effects as those of embodiment 5.

In this embodiment, the shared memory units 114 are interconnected viaaccess path a2 (140) and the cache memory units 115 via access path b2(141) to make a dual system; however, instead, the same dual systemeffect can be obtained by writing the same data in both the sharedmemory units 114 or both the cache memory units 115 from the channelinterface units 111, disk interface units 112, or SM selector units 113or CM selector units 123. In this case, it is unnecessary tointerconnect the shared memory units 114 or cache memory units viaaccess path a2 (140) or access path b2 (141). However, if they areinterconnected with access path a2 (140) or access path b2 (141), thedata in the two shared memory units 114 or the two cache memory units115 can be directly cross-checked for confirmation or a similar purpose,resulting in improved reliability.

FIG. 74 shows a variation in which one cluster contains two sharedmemory packages 14 and two cache memory packages 15, where a set whichconsists of one shared memory package 14 and one cache memory package 15is mounted on each of the two areas of the interface platter 2 dividedby a power supply boundary 300, as in embodiment 6.

This produces the same effects as those of embodiment 6.

Although each of the two clusters contains shared memory packages 14 andcache memory packages 15 in this example, it is also acceptable that onecluster contains all the shared memory packages 14 and cache memorypackages 15 used in the disk array controller 1 while the other clusterhas no shared memory package 14 nor cache memory package 15.

Embodiment 17

FIGS. 75 and 77 show another embodiment in which the disk arraycontroller 1 of embodiment 12 in FIG. 64 is mounted in the rack.

FIG. 75 illustrates how packages are mounted on platters and how theplatters are positioned and interconnected. Each interface platter 2bears two channel interface packages 11 and two disk interface packages12, which constitute one selector group 150. The selector units (SMselector units) 113 connected to the shared memory packages, and theselector units (CM selector units) 123 connected to the cache memorypackages are mounted on the backside of the interface platters 2. Thisarrangement can decrease the required width of the interface platters 2.Two interface platters make up a redundant system 155.

The disk array controller 1 has eight interface platters 2 which make upfour redundant systems 155. One memory platter 3 bears one shared memorypackage 14 and two cache memory packages 15. To make a dual memorysystem, two memory platters 3 are provided.

Between two interface platters which constitute a redundant system, thechannel interface packages 11 and disk interface packages 12 areconnected with the SM selector units 113 and CM selector units 123 bycable a0 (4-5) and cable b0 (4-6), respectively.

Here, when two cables a0 (4-5) and two cables b0 (4-6) are used and oneof the two cables is used for the access path to connect the interfaceunits within one selector group 150 with the selector units within theother selector group 150, and the other cable is used for the accesspath to connect the selector units within the former selector group 150with the interface units within the latter selector group 150, even ifone of the access paths fails, the cable a0 (4-5) or cable b0 (4-6) canbe replaced without affecting the other access path.

Each interface platter 2 is connected with four cables from two memoryplatters 3, where one cable a1 (4-7) and one cable b1 (4-8) come fromeach memory platter. This means that each memory platter is connectedwith a total of 16 cables from eight interface platters 2, where onecable a1 (4-7) and one cable b1 (4-8) come from each interface platter.The memory platters 3 are interconnected by cable a2 (4-10) and cable b2(4-11).

Connectors for the cables which interconnect the platters are located onthe backside of the platters, where the inter-platter cables areconnected. This eliminates the need for detouring the inter-plattercables around the cables (not shown) for connection with the hostcomputer 101 at the sub edge side of the channel interface packages 11(opposite to the side where the packages are connected with theplatters) or the cables (not shown) for connection with the magneticdisk drives 120 at the sub edge side of the disk interface packages 12,shortening the required cable length.

As mentioned earlier, the cables used here are expensive. Datatransmission at high frequencies by cables could cause noise, whichoften makes the implementation difficult. For this reason, to shortenthe cable length offers a great advantage.

In this embodiment, the interface platters 2 and memory platters 3 arevirtually perpendicular to each other. This makes it possible to locatethe connectors for the cables which connect the interface platters 2 andmemory platters 3 so that the cables can be shortened as shown in FIG.75.

FIG. 75 shows that the interface platters 2 are vertical to thehorizontal plane and the memory platters 3 are parallel to thehorizontal plane; however, they may be oriented vice versa.

Also as shown in FIG. 75, the interface platters 2 may be located sothat the memory platters 3 are sandwiched by them. This can also shortenthe cables which connect the interface and memory platters.

FIG. 77 shows the platters in FIG. 75 which is housed in the rack 180.The platters bearing the packages are located on the front side in therack and power supplies 0 (170) and 1 (171) are located behind them.

The power supplies 0 (170) and 1 (171) are separately connected with theplatters, which facilitates power supply control during platterreplacement.

As shown in FIG. 77, power may be supplied to each platter from a dualpower supply system consisting of a power supply 0 (170) and a powersupply 1 (171). When such a dual power supply system is used, even ifone of the power supplies fails, the other power supply is used;therefore, it is unnecessary to shut down the packages on the platterwhich has been energized by the defective power supply, decreasing thenumber of system components to be stopped in case of failure.

Embodiment 18

FIGS. 76 and 78 show an embodiment in which the disk array controller 1of embodiment 12 in FIG. 28 is mounted in the rack.

FIG. 76 illustrates how packages are mounted on platters and how theplatters are positioned and interconnected. Each interface platter 2bears two channel interface packages 11 and two disk interface packages12, which constitute one selector group 150, as well as one sharedmemory package 14 and one cache memory package 15. The selector units(SM selector units) 113 connected to the shared memory packages, and theselector units (CM selector units) 123 connected to the cache memorypackages are mounted on the backside of the interface platters 2. Thiscan reduce the required width of the interface platters 2. Two interfaceplatters make up a redundant system 155. The disk array controller 1 hastwo interface platters 2 which make up one redundant system 155.

Between two interface platters which constitute a redundant system 155,the channel interface packages 11 and disk interface packages 12 areconnected with the SM selector units 113 and CM selector units 123 bycable a0 (4-5) and cable b0 (4-6), respectively.

Here, when two cables a0 (4-5) and two cables b0 (4-6) are used and oneof the two cables is used for the access path to connect the interfaceunits within one selector group 150 with the selector units within theother group 150 and the other cable is used for the access path toconnect the selector units within the former selector group 150 with theinterface units within the latter selector group 150, even if one of theaccess paths fails, the cable a0 (4-5) or cable b0 (4-6) can be replacedwithout affecting the other access path.

Between the platters, the SM selector units 113 and CM selector units123 are connected with the shared memory units 114 and cache memoryunits 115 by two cables a1 (4-7) and two cables b1 (4-8), respectively.The two shared memory units 113 as a dual system and the two cachememory units 115 as a dual system are interconnected by cable a2 (4-10)and cable b2 (4-11), respectively. Therefore, the two interface plattersare interconnected by a total of eight cables. However, the number ofcables which can be used here is not limited as above.

Connectors for the cables which interconnect the platters are located onthe backside of the platters, where the inter-platter cables areconnected. This eliminates the need for detouring the inter-plattercables around the cables (not shown) for connection with the hostcomputer 101 at the sub edge side of the channel interface packages 11(opposite to the side where the packages are connected with theplatters) or the cables (not shown) for connection with the magneticdisk drives 120 at the sub edge side of the disk interface packages 12,shortening the required cable length.

The interface platters 2 may be vertically arranged as shown in FIG. 76.This arrangement can shorten the cable length required to interconnectthe platters.

FIG. 78 shows the platters in FIG. 76 which is housed in the rack 180.The platters bearing the packages are located on the front side in therack and power supplies 0 (170) and 1 (171) are located behind them.

The power supplies 0 (170) and 1 (171) are separately connected with theplatters, which facilitates power supply control during platterreplacement.

As shown in FIG. 78, power may be supplied to each platter from a dualpower supply system consisting of one power supply 0 (170) and one powersupply 1 (171). When such a dual power supply system is used, even ifone of the power supplies fails, the other power supply can be used;therefore, it is unnecessary to shut down the packages on the platterwhich has been energized by the defective power supply, decreasing thenumber of system components to be stopped in case of failure.

Embodiment 19

FIGS. 79 and 80 show another embodiment in which the disk arraycontroller 1 of embodiment 12 in FIG. 28 is mounted in what is called a19-inch rack (185).

FIG. 79 illustrates the disk array controller 1 housed in a 19-inch rack185. Each MP box 250 houses channel interface packages 11, diskinterface packages 12, a shared memory (SM) selector package 13 and acache memory (CM) selector package 23. Shared memory packages 14 andcache memory packages 15 are housed in an MEM box 251. All powersupplies are housed in a PS box 252. Thus, the disk array controller 1consists of four MP boxes 250, one MEM box 251 and one PS box 252.

FIG. 81 shows, as an example, how channel interface packages 11, diskinterface packages 12, SM selector packages 13 and CM selector packages23 are housed in an MP box 250. One interface platter 2 bears a selectorgroup 150 which consists of two channel interface packages 11, two diskinterface packages 12, one SM selector package 13 and one CM selectorpackages 23.

Each interface platter is connected with two cables a1 (4-7) forconnecting an SM selector package 13 with shared memory packages 14 andtwo cables b1 (4-8) for connecting a CM selector package 23 with cachememory packages 15.

One MP box 250 houses two interface platters 2 which constitute aredundant system 155. These two interface platters 2 are interconnectedby cable a0 (4-5) and cable b0 (4-6) as shown in FIG. 80 to make up aredundant system.

Here, when two cables a0 (4-5) and two cables b0 (4-6) are used and oneof the two cables is used for the access path to connect the interfaceunits within one selector group 150 with a selector unit within theother selector group 150 and the other cable is used for the access pathto connect a selector unit within the former selector group 150 with theinterface units within the latter selector group 150, even if one of theaccess paths fails, the cable a0 (4-5) or cable b0 (4-6) can be replacedwithout affecting the other access path.

Four cables 302 for connection with the host computer 101 are connectedat the sub edge side (opposite to the side where the packages areconnected with the platters) of each channel interface package 11, andfour cables 301 for connection with the magnetic disk drives 120 areconnected at the sub edge side of each disk interface package 12.

FIG. 82 shows, as an example, how shared memory packages 14 and cachememory packages 15 are housed in the MEM box 251. One memory platterbears two packages: one shared memory package 14 and one cache memorypackage 15.

Each memory platter 3 is connected with eight cables: cables a1 (4-7)for connection between the SM selector packages 13 and shared memorypackages 14 and cables b1 (4-8) for connection between the CM selectorpackages 23 and cache memory packages 15.

To make a dual memory system, two memory platters 3 are housed in theMEM box 251 and the two memory platters 3 are interconnected by cable a2(4-10) and cable b2 (4-11) as shown in FIG. 80.

FIG. 83 shows, as an example, how power supplies are housed in the PSbox 252. To one MP box, power is supplied from MP box power supplygroups 175 each of which is composed of six power supply modules 172.The six power supply modules in each group constitute two 3-module setsto make a dual system. Power is supplied to one MEM box from an MEM boxpower supply group 176 composed of four power supply modules 172. Thesefour power supply modules 172 constitute two 2-module sets to make adual system. To back up the shared memory units 114 and cache memoryunits 115 in case of power failure, two memory backup batteries 177 areprovided.

Because the disk array controller 1 consists of four MP boxes 250 andone MEM box 251, the PS box 252 houses four MP box power supply groups175 and one MEM box power supply group 176.

FIG. 80 illustrates inter-platter cable connections. Between twointerface platters constituting a redundant system, the channelinterface packages 11 and disk interface packages 12 are connected withthe SM selector units 113 and CM selector units 113 by cable a0 (4-5)and cable b0 (4-6), respectively.

Each interface platter 2 is connected with a total of four cables fromtwo memory platters 3 where one cable a1 (4-7) and one cable b1 (4-8)come from each memory platter. Therefore, each memory platter 3 isconnected with a total of 16 cables from eight interface platters 2,where one cable a1 (4-7) and one cable b1 (4-8) come from each interfaceplatter.

The two memory platters 3 are interconnected by cable a2 (4-10) andcable b2 (4-11) to make a dual system of shared memory units 114 and adual system of cache memory units 115.

The interface platters 2 are located so that the memory platters 3 aresandwiched by them. This can also shorten the cables which connect theinterface and memory platters.

When the interface packages, memory packages and power supplies arehoused in their respective boxes and the boxes are housed in the rack asmentioned above, the disk array controller 1 can be serviced box by boxand thus its maintenance is easier.

In addition, a commercially available 19-inch rack can be used for thedisk array controller, so it is possible to configure a workstation,server or other system housed in a 19-inch rack which includes storages.

So far, the best modes for embodying the invention have been explainedusing various embodiments. The invention may be embodied in otherspecific forms. For instance, in embodiments where channel interfaceunits and disk interface units are not connected via shared buses, it isalso possible to mount the channel interface packages and disk interfacepackages on different platters as mentioned for embodiment 1. Inembodiments which have both shared memory units and cache memory units,it is also possible to mount the shared memory packages and cache memorypackages on different platters. The above explanations have been madefor a disk array controller which uses magnetic disk drives, butDVD-RAMs, magnet-optical disks, magnetic tape or other storages may beused in place of magnetic disk drives.

According to this invention, even if one platter fails, only componentsfor which the packages mounted on that platter are responsible have tobe stopped and a defective part on the platter can be replaced withoutstopping the entire system; in other words, faults can be remediedwithout stopping the system so that the system can be operated withoutinterruption around the clock, all the year round.

In addition, to cope with the increase or decrease in the number ofplatters bearing interface packages, the performance of internal busescan be made scalable. Therefore, scalability of performance and capacityis assured to suit a wide range of systems from small to large systemswithout unfavorably affecting the cost performance. Besides, it becomespossible to supply products at reasonable prices which match the scaleof the system.

1. A disk array controller comprising: a channel interface package inwhich at least a channel interface unit with a host computer and anaccess path interface unit are packaged; a disk interface package inwhich at least a disk interface with a disk drive and an access pathinterface unit are packaged: a memory package in which a memory unit forstoring control data for the disk drive and an access path interfaceunit are packaged, wherein connections are made between the access pathinterface unit in the channel interface package and the access pathinterface unit in the memory package and between the access pathinterface unit in the disk interface package and the access pathinterface unit in the memory package by cables; and a platter, whereinthe channel interface package and the disk interface package are mountedon the platter, wherein a first path and a second path are printed onthe platter, wherein the first path couples the channel interfacepackage to the cables, and wherein the second path couples the diskinterface package to the cable.
 2. A disk array controller comprising: achannel interface package in which at least a channel interface unitwith a host computer and an access path interface unit are packaged; adisk interface package in which at least a disk interface with a diskdrive and an access path interface unit are packaged: a memory packagein which a memory unit for storing control data for the disk drive andan access path interface unit are packaged, wherein connections are madebetween the access path interface unit in the channel interface packageand the access path interface unit in the memory package and between theaccess path interface unit in the disk interface package and the accesspath interface unit in the memory package by cables; first and a secondplatters; a first cable coupling the channel interface package and thememory packages; and a second cable coupling the disk interface packageand the memory package, wherein the channel interface package is mountedon the first platter, and the disk interface package is mounted on thesecond platter, wherein a path coupling the channel interface package tothe cable is printed on the first platter, and wherein a path couplingthe disk interface package and the cable is printed on the secondplatter.
 3. A disk array controller comprising: a channel interface unitto be coupled with a host computer; a disk interface unit to be coupledwith a disk drive; a memory unit for storing control data for the diskdrive; a first platter on which the channel interface unit is mounted; asecond platter on which the disk interface unit is mounted; a thirdplatter on which the memory unit is mounted; a first cable which couplesthe first and third platters: a second cable which couples the secondand third platters, wherein a path coupling the channel interface unitto the first cable is printed on the first platter, wherein a pathcoupling the memory unit to the first cable is printed on the thirdplatter, wherein a path coupling the memory unit to the second cable isprinted on the third platter; a cache memory unit for storing data to berecorded into the disk drive; a fourth platter on which the cache memoryunit is mounted; a third cable which couples the first and fourthplatters; and a fourth cable which couples the second and fourthplatters, wherein a path coupling the cache memory unit to the thirdcable is printed on the fourth platter, and wherein a path coupling thecache memory unit to the fourth cable is printed on the fourth platter.